type row is array ( 0 to 7) of std_logic; signal x1 :row; si

type row is array ( 0 to 7) of std_logic; signal x1 :row; signal y1:std_logic_vector(0 to 7);
x1(0 to3)

--定义matrix_index 为数组
TYPE matrix_index is array (3 downto 0) of std_logic_vector(7 downto 0);
SIGNAL a:matrix_index;--定义了数组a[4],即数组元素为a[0],a[1],a[2],a[3]
constant R :matrix_index:=( x"15",x"0F",x"0A",x"06");--定义了常数数组R[4]
--使用时跟C语言中一样,加下标就可以了,上面是用downto定义了方向,故R[0]是最后一项,如在R数组中R[0]=X"06",R[3]=X"15"
以上不知道说清楚了没,
我看还是补充一段参考程序吧
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY shift_row_inv IS
PORT(
shiftrow_in :IN STD_LOGIC_VECTOR(127 DOWNTO 0);
shiftrow_out :OUT STD_LOGIC_VECTOR(127 DOWNTO 0)
);
END shift_row_inv;
ARCHITECTURE beh OF shift_row_inv IS
-- type describing the byte array consisting of 16 byte matrix array
TYPE matrix_index is array (15 downto 0) of std_logic_vector(7 downto 0);
SIGNAL b,c :matrix_index;
BEGIN
--initial mapping of input into a byte matrix array named b
matrix_mapping:PROCESS(shiftrow_in)
BEGIN
FOR i IN 15 DOWNTO 0 LOOP
\x05b(15-i) <= shiftrow_in(8*i+7 DOWNTO 8*i);
END LOOP;
END PROCESS matrix_mapping;
--shift row transformation
--\x05 b(i)\x05 -->\x05\x05c(i)
--
-- | 0 4 8 12 | | 0 4 8 12 | (no shift)
-- | 1 5 9 13 | ==> | 13 1 5 9 | ( 1 right shift)
-- | 2 6 10 14 | | 10 14 2 6 | ( 2 right shift)
-- | 3 7 11 15 | | 7 11 15 3 | ( 3 right shift)
--shifted first column
c(0) <= b(0);
c(1) <= b(13);
c(2) <= b(10);
c(3) <= b(7);
--shifted second column
c(4) <= b(4);
c(5) <= b(1);
c(6) <= b(14);
c(7) <= b(11);
--shfited third column
c(8) <= b(8);
c(9) <= b(5);
c(10) <= b(2);
c(11) <= b(15);
--shifted forth column
c(12) <= b(12);
c(13) <= b(9);
c(14) <= b(6);
c(15) <= b(3);
--mapping temporary c vector into shiftedrow output
matrix_mapping_back:PROCESS(c)
BEGIN
FOR i IN 15 DOWNTO 0 LOOP
\x05shiftrow_out(8*i+7 DOWNTO 8*i) <= c(15-i);
END LOOP;
END PROCESS matrix_mapping_back;
END beh;