搜搜做题作业网英语翻译VBMAR router adopts a concurrent architecture.Any physic
来源：学生作业帮 编辑：搜搜做题作业网作业帮 分类：英语作业 时间：2024/04/27 17:30:45
英语翻译
VBMAR router adopts a concurrent architecture.Any physical channel except the one connecting to local processor is shared by two virtual channels.Each virtual channel is implemented as a data bus inside the router.So two data buses serve one physical channel.A control pipeline is set for each physical channel,which controls the moving of a message through the router.Thus multiple messages can be routed simultaneously.A control pipeline includes three stages,input control logic,routing control logic,and output control logic.Each stage drains a clock cycle.Message moves in the router stage by stage under control.A data bus is actually a data pipeline.A message spends 3 clock cycles to go through a router when no blocking exists.This concurrent architecture can improve the network throughput greatly than the commonly used single control logic architecture.
求不复制百度和google的翻译，真心求大神翻译！
VBMAR router adopts a concurrent architecture.Any physical channel except the one connecting to local processor is shared by two virtual channels.Each virtual channel is implemented as a data bus inside the router.So two data buses serve one physical channel.A control pipeline is set for each physical channel,which controls the moving of a message through the router.Thus multiple messages can be routed simultaneously.A control pipeline includes three stages,input control logic,routing control logic,and output control logic.Each stage drains a clock cycle.Message moves in the router stage by stage under control.A data bus is actually a data pipeline.A message spends 3 clock cycles to go through a router when no blocking exists.This concurrent architecture can improve the network throughput greatly than the commonly used single control logic architecture.
求不复制百度和google的翻译，真心求大神翻译！
vbmar路由器采用并行体系结构.除了一个连接到本地处理器的任何物理信道是由两个虚拟信道共享.每个虚拟信道是作为一个数据总线在路由器上的实现.于是两个数据总线为一个物理信道.控制管路设置为每个物理信道,控制运动的消息通过路由器.因此,可以同时发送多个消息.控制管道分为三个阶段,输入控制逻辑,路由控制逻辑,并输出控制逻辑.一个时钟周期的每一阶段排水.消息的移动路由器逐级控制.数据总线实际上是一个数据管道.消息在3个时钟周期要经过一个路由器时存在的无阻塞.这种并行架构可以大大高于常用的单一控制逻辑结构,提高了网络的吞吐量.
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