英语翻译The divider circuit 14 (division factor a·n/m) shown in
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英语翻译
The divider circuit 14 (division factor a·n/m) shown in FIG.1may pass a·n = 2 clock cycles in a frame of m = 8,7,or 5clock cycles of the first clock signal,respectively,e.g.by using a clock gate (and a counter).
The divider circuit 14 (division factor a·n/m) shown in FIG.1may pass a·n = 2 clock cycles in a frame of m = 8,7,or 5clock cycles of the first clock signal,respectively,e.g.by using a clock gate (and a counter).
图1中 14 是除法电路,表达式为 a·n/m.比如利用时钟脉冲们或计数器控制,在m分别为8、7或5个时钟周期信号时,a·n为两个时钟周期.
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