Error (10228):Verilog HDL error at top.v(1):module "top" can
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Error (10228):Verilog HDL error at top.v(1):module "top" cannot be declared more than once
晕
晕
貌似 叫top 的module 被命名了不知一次
Error (10228):Verilog HDL error at top.v(1):module "top" can
Error (10170):Verilog HDL syntax error at mpeg2_ts_tb.v(1) n
Error (10170): Verilog HDL syntax error at Verilog1.v(10) ne
Error (10170):Verilog HDL syntax error at Verilog1.v(2) near
Error (10170):Verilog HDL syntax error at ***.v(222) near te
Error (10278):Verilog HDL Port Declaration error at led_disp
Verilog HDL错误Error (10110)
Error:Top-level design entity "Verilog1" is undefined
verilog HDL
(at the top of,at top of.in the top of)the mountain you can
syntax error at line
Error (10327):VHDL error at Vhdl1.vhd(16):can't determine de